A conventional MESFET (hereinafter, also simply referred to as “FET”) will be described with reference to FIG. 11A, FIG. 11B, FIG. 11C, FIG. 12A and FIG. 12B. FIG. 11A shows a cross-sectional view of the structure of a MESFET in the ON-state, formed on a GaAs semi-insulating substrate, FIG. 11B shows an equivalent circuit diagram corresponding to FIG. 11A, FIG. 11C shows a circuit diagram when the FET in FIG. 11A is switched, FIG. 12A shows a cross-sectional view of the structure in the OFF-state and FIG. 12B shows an equivalent circuit diagram corresponding to FIG. 12A.
In FIG. 11A and FIG. 11B, numeral 10a denotes a source electrode. Numeral 10b denotes a drain electrode. Numeral 11a denotes a Schottky gate electrode. Numeral 21 denotes a GaAs ohmic contact layer. Numeral 22 denotes an AlGaAs undoped layer. Numeral 23 denotes an AlGaAs active layer. Numeral 24 denotes a buffer layer in which AlGaAs layers and GaAs layers are laminated alternately and numeral 25 denotes the GaAs semi-insulating semiconductor substrate. In addition, numeral 27a denotes a depletion layer.
Moreover, Cgs_on indicates the gate-source capacitance in the ON-state. Cgd_on indicates the gate-drain capacitance in the ON-state. Cds_on indicates the drain-source capacitance in the ON-state. Rch indicates the channel resistance in the ON-state. Rc1 indicates the contact resistance between the source electrode 10a and the ohmic contact layer 21. Rc2 indicates the contact resistance between the drain electrode 10b and the ohmic contact layer 21. Rin1 indicates the resistance component existing between the source and the gate other than Rch and Rin2 indicates the resistance component existing between the drain and the gate other than Rch.
In FIG. 11C, numeral 30a denotes the FET. Numerals 40a, 40b and 41a denotes bias resistances. Numeral 50 denotes an input terminal. Numeral 51 denotes an output terminal. Numeral 52 denotes a drain-source bias terminal and numeral 53 denotes a gate bias terminal.
FIG. 12A shows a cross-sectional view of the structure of the FET 30a in the OFF-state. FIG. 12A is different from FIG. 11A in that Cgs_off indicates the gate-source capacitance in the OFF-state, Cgd_off indicates the gate-drain capacitance in the OFF-state and Cds_off indicates the drain-source capacitance in the OFF-state and that Rch is so high that it is negligible in the equivalent circuit.
The gate width of the FET 30a shown in the conventional example is 1 mm and the gate electrode 11a has a gate length of 0.5 μm. A standard value of Rch is 1.0 Ω/mm.
Next, a method for switching the conventional FET configured as above will be described.
First, in order to turn the FET on, a voltage of 0 V is applied to the drain-source bias terminal 52 and a voltage of 0V or a positive voltage not higher than the Schottky barrier potential (about 0.7 V) is applied to the gate bias terminal 53. Thus, the FET 30a becomes forward biased and is turned on between the drain and the source. At this time, as shown in FIG. 11A, the channel of the FET 30a is opened and transmission of signals becomes possible, so that signals can be transmitted from a point A to a point B.
At this time, as shown in FIG. 11B, the equivalent circuit for a region underneath the gate of the FET can be represented by a circuit in which a series capacitance of Cgs_on and Cgd_on is connected in parallel with Cds_on and Rch. Usually, in frequency bands used for mobile communications, the impedance of Rch is much lower than those of the capacitance components and is dominant. In the conventional example, the on-resistance (Ron) that indicates the sum of the resistance components within the FET in the ON-state is about 1.5 Ω.
The insertion loss, which represents the characteristics of a switching circuit in the ON-state, is proportional to Ron. Among the resistance components constituting Ron, Rch is most dominant, so that it is effective to decrease Rch in order to reduce the insertion loss. Generally, the shorter the gate length of the FET is or the larger the gate width Wg is, or the higher the concentration in the active layer is, the lower becomes Rch. At the same time, however, not only Cgs_on, Cgd_on and Cds_on but also Cgs_off, Cgd_off and Cds_off, which are the capacitances in the OFF-state, become higher.
On the other hand, as shown in FIG. 12A, in order to turn off the FET, the gate-source potential is set to the threshold potential of the FET or less, while keeping the potentials at the drain terminal and the source terminal unchanged. Thus, the channel of the FET closes and the FET is turned off. FIG. 12B shows the equivalent circuit of the FET in the OFF-state, from which it can be understood that a parallel capacitance of the series capacitance of Cgs_off and Cgd_off, and Cds_off is dominant in the OFF-state. For example, in the case of an FET having a gate width of 1 mm, the sum of the above-mentioned capacitances is about 0.1 pF. Isolation characteristics, which indicate the characteristics of the switching circuit in the OFF-state, represent the leakage of signals from input to output, and as the capacitance components between input and output increase, the isolation characteristics deteriorate.
However, in the conventional configuration described above, if the gate length is shortened to decrease the on-resistance for the purpose of reducing the insertion loss, then Cds increases. Moreover, if the concentration in the active layer is increased or the gate width is increased, then Cgs and Cgd also increase in addition to Cds. Therefore, the insertion loss in high frequency bands deteriorates and further, the isolation characteristics also deteriorate.
Moreover, also when the FET is used while being connected in parallel with a signal path, there is the problem that the insertion loss of the on-path deteriorates because of the increase in the capacitance component of the off-path.